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Journal papers
[J16] M.G. Moghaddam and C. Ababei, Performance evaluation of Network-on-Chip based H.264 video decoders via full system simulation, IEEE Embedded Systems Letters, 2017.
[J15] P. Irgens, C. Bader, T. Le, D. Saxena, and C. Ababei, An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm, Elsevier Journal HardwareX, 2017.
[J14] C. Ababei, S. Duerr, J. Ebel, R. Marineau, M.G. Moghaddam and T. Sewell, Open source digital camera on field programmable gate arrays, Int. Journal of Handheld Computing Research (IJHCR), Special issue on IEEE Int. Conf. on Electro Information Technology (EIT), vol. 7, no. 4, Oct.-Dec. 2016.
[J13] S. Duerr, C. Ababei, and D.M. Ionel, SmartBuilds: an energy and power simulation framework for buildings and districts, IEEE Trans. on Industry Applications, 2016.
[J12] A.Y. Yamamoto and C. Ababei, Unified reliability estimation and management of NoC based chip multiprocessors, Elsevier Microprocessors and Microsystems, vol. 38, no. 1, pp. 53-63, Feb. 2014.
[J11] H. Sajjadi Kia and C. Ababei, A new reliability evaluation methodology with application to lifetime oriented circuit design, IEEE Trans. on Device and Materials Reliability, vol. 13, no. 1, pp. 192-202, March 2013.
[J10] B.-R.V. Vinnakota and C. Ababei, Determination of the minimum break point set of directional relay networks based on k-trees of the network graphs, IEEE Trans. on Power Delivery, vol. 26, no. 4, pp. 2318-2323, Oct. 2011.
[J9] C. Ababei and R. Kavasseri, Efficient network reconfiguration using minimum cost maximum flow based branch exchanges and random walks based loss estimations, IEEE Trans. on Power Systems, vol. 26, no. 1, pp. 30-37, Feb. 2011.
[J8] V. de Paulo and C. Ababei, 3D Network-on-Chip architectures using homogeneous meshes and heterogeneous floorplans, Hindawi Int. Journal of Reconfigurable Computing (IJRC) - Special Issue on Int. Conference on Reconfigurable Computing and FPGAs (ReconFig 2009), 2010.
[J7] C. Ababei, S. Yuvarajan, and D.L. Schulz, Toward integrated PV panels and power electronics using printing technologies, Elsevier Solar Energy, vol. 84, pp. 1111-1123, 2010.
[J6] C. Ababei, Speeding up FPGA placement via partitioning and multithreading, Hindawi Int. J. of Reconfigurable Computing (IJRC), 2009.
[J5] G. Wang, S. Sivaswamy, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh, Statistical analysis and design of HARP routing pattern FPGAs, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 10, pp. 2088-2102, Oct. 2006.
[J4] C. Ababei, H. Mogal, and K. Bazargan, Three-dimensional place and route for FPGAs, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 6, pp. 1132-1140, June 2006.
[J3] C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, K. Bazargan, and S.S. Sapatnekar, Placement and routing in 3D integrated circuits, IEEE Design and Test, vol. 22, no. 6, pp. 520-531, Nov.-Dec. 2005.
[J2] C. Ababei and K. Bazargan, Non-contiguous linear placement for reconfigurable fabrics, Int. Journal of Embedded Systems, Issue 4/5, Interscience Publishers, 2005.
[J1] P. Maidee, C. Ababei, and K. Bazargan, Timing-driven partitioning-based placement for island style FPGAs, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 3, pp. 395-406, Mar. 2005.

Conference, symposium, workshop, and poster papers
[C39] I.J. Barge and C. Ababei, A network-on-chip based H.264 video decoder prototype implemented on FPGAs, IEEE Int. Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, Apr. 2017.
[C38] M.G. Moghaddam and C. Ababei, Investigation of DVFS for Network-on-Chip based H.264 video decoders with truly real workload, IEEE Energy-efficient Networks of Computers (E2NC): from the Chip to the Cloud, Int. Green and Sustainable Computing Conference (IGSC), Hangzhou, China, Nov. 2016.
[C37] N. Zimmerman, K. Carey, and C. Ababei, On aerial indoor position control and system integration for quadcopters using lidars, ASME Dynamic Systems and Control Conf. (DSCC), Minneapolis, MN, Oct. 2016.
[C36] C. Ababei, S. Duerr, J. Ebel, R. Marineau, M.G. Moghaddam, and T. Sewell, Open source digital camera on field programmable gate arrays, IEEE Int. Conf. on Electro Information Technology (EIT), Grand Forks, ND, May 2016.
[C35] M.G. Moghaddam, A. Yamamoto, and C. Ababei, Investigation of DVFS based dynamic reliability management for chip multiprocessors, IEEE Int. Workshop on Dependable Many-Core Computing (DMCC), Amsterdam, Netherlands, July 2015.
[C34] S. Duerr, C. Ababei, and D.M. Ionel, SmartBuilds: an energy and power simulation framework for buildings and districts, IEEE Energy Conversion Congress and Exposition (ECCE), Montreal, Canada, Sep. 2015.
[C33] H. Sajjadi Kia, C. Ababei, S. Srinivasan, and S. Jabeen, A new scalable fault tolerant routing algorithm for networks-on-chip, IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, Aug. 2015.
[C32] C. Ababei, R. Kavasseri, and M. Zare, Net reordering and multicommodity flow based global routing for FPGAs, IEEE Int. Conf. on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, Dec. 2014.
[C31] M. Zare, R. Kavasseri, and C. Ababei, FPGA-based design and implementation of direct torque control for induction machines, IEEE Int. Conf. on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, Dec. 2014.
[C30] C. Ababei and N. Mastronarde, Benefits and costs of prediction based DVFS for NoCs at router level, IEEE Int. SoC Conference (SOCC), Las Vegas NV, Sep. 2014.
[C29] C. Ababei and C. Tamma, Distributed minimum energy point tracking for systems-on-chip, IEEE Int. Conf. on Electro Information Technology (EIT), Milwaukee, WI, May 2014.
[C28] H. Sajjadi Kia, M. Zare, R. Kavasseri, and C. Ababei, Dynamic simulation of direct torque control of induction motors with FPGA based accelerators, IEEE Int. Conference on Reconfigurable Computing and FPGAs (ReConFig 2013), Cancun, Mexico, Dec. 2013.
[C27] A.Y. Yamamoto and C. Ababei, Unified system level reliability evaluation methodology for multiprocessor systems-on-chip, IEEE International Green Computing Conference, Lighter-than-Green Dependable Multicore Architectures Workshop, San Jose, CA, June 2012.
[C26] H. Sajjadi Kia and C. Ababei, A new reliability evaluation methodology and its application to Network-on-Chip routers, IFIP/IEEE Int. Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz CA, Oct. 2012.
[C25] H. Sajjadi Kia and C. Ababei, Efficient high-speed current-mode links for network-on-chip performance optimization, IEEE Int. SoC Conference (SOCC), Niagara Falls NY, Sep. 2012.
[C24] R. Katti and C. Ababei, Secure comparison without explicit XOR, Ninth European Dependable Computing Conference, Sibiu, Romania, May 2012.
[C23] H. Sajjadi Kia and C. Ababei, Improving fault tolerance of Network-on-Chip links via minimal redundancy and reconfiguration, IEEE Int. Conference on Reconfigurable Computing and FPGAs (ReConFig 2011), Cancun, Mexico, Dec. 2011.
[C22] H. Sajjadi Kia and C. Ababei, A new fault-tolerant and congestion-aware adaptive routing algorithm for regular Networks-on-Chip, IEEE Congress on Evolutionary Computation (CEC), New Orleans LA, June 2011.
[C21] C. Ababei, H. Sajjadi Kia, O.P. Yadav, and J. Hu, Energy and reliability oriented mapping for regular Networks-on-Chip, ACM/IEEE Int. Symposium on Networks-on-Chip (NOCS), Pittsburg PA, May 2011.
[C20] C. Ababei, Efficient congestion-oriented custom Network-on-Chip topology synthesis, IEEE Int. Conference on Reconfigurable Computing and FPGAs (ReConFig 2010), Cancun, Mexico, Dec. 2010.
[C19] C. Ababei, Network-on-Chip design and optimization using specialized influence models, ACM/IEEE Design Automation Conference (DAC), Anaheim CA, June 2010.
[C18] C. Ababei and R. Kavasseri, Efficient extreme event screening for power systems using constrained and unbalanced partitioning, IEEE PES General Meeting, Minneapolis MN, July 2010.
[C17] C. Ababei and R. Kavasseri, Speeding-up network reconfiguration by minimum cost maximum flow based branch exchanges, IEEE PES Transmission and Distribution Conference and Exposition, New Orleans LA, Apr. 2010.
[C16] V. de Paulo and C. Ababei, A framework for 2.5D NoC exploration using homogeneous networks over heterogeneous floorplans, IEEE Int. Conference on Reconfigurable Computing and FPGAs (ReConFig 2009), Cancun, Mexico, Dec. 2009.
[C15] C. Ababei and R. Katti, Achieving Network-on-Chip fault tolerance by adaptive remapping, IEEE Int. Parallel and Distributed Processing Symposium (IPDPS), Reconfigurable Architectures Workshop (RAW), Rome, Italy, May 2009.
[C14] C. Ababei, Parallel placement for FPGAs revisited, IEEE ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA), Monterey CA, Feb. 2009.
[C13] C. Ababei, H. Mogal, and K. Bazargan, 3D FPGAs: placement, routing and architecture evaluation, IEEE ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA), Monterey CA, Feb. 2005.
[C12] S. Sivaswamy, G. Wang, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh, HARP: hard-wired routing pattern FPGAs, IEEE ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA), Monterey CA, Feb. 2005.
[C11] C. Ababei, H. Mogal, and K. Bazargan, Three-dimensional place and route for FPGAs, ACM/IEEE Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 773-778, 2005.
[C10] C. Ababei, P. Maidee, and K. Bazargan, Exploring potential benefits of 3D FPGA integration, Field-Programmable Logic and its Applications (FPL), 2004.
[C9] C. Ababei and K. Bazargan, Non-contiguous linear placement for reconfigurable fabrics, IEEE Int. Parallel and Distributed Processing Symposium (IPDPS), Reconfigurable Architectures Workshop (RAW), Santa Fe NM, 2004.
[C8] C. Ababei and K. Bazargan, Placement method targeting predictability robustness and optimality, ACM/IEEE Int. Conference on Computer-Aided Design (ICCAD), pp. 81-85, 2003.
[C7] P. Maidee, C. Ababei, and K. Bazargan, Fast timing-driven partitioning-based placement for island style FPGAs, ACM/IEEE Design Automation Conference (DAC), pp. 598-603, 2003. Nominated for best paper award.
[C6] C. Ababei and K. Bazargan, Timing minimization by statistical timing hMetis-based partitioning, Int. Conference on VLSI Design, pp. 58-63, 2003.
[C5] C. Ababei, N. Selvakkumaran, K. Bazargan, and G. Karypis, Multi-objective circuit partitioning for cut-size and path-based delay minimization, ACM/IEEE Int. Conference on Computer-Aided Design (ICCAD), pp. 81-85, 2002.
[C4] C. Ababei and K. Bazargan, Statistical timing driven partitioning for VLSI circuits, ACM/IEEE Design Automation and Test in Europe Conference (DATE), 2002.
[C3] C. Ababei and R. Marculescu, Low-power realizations of secure chaotic communication schemes, IEEE Asia Pacific Conference on Circuits and Systems, 2000.
[C2] C. Ababei and R. Marculescu, V. Sundarajan, Probabilistic aspects of crosstalk in CMOS ICs, IEEE Custom Integrated Circuits Conference (CICC), 2000.
[C1] R. Marculescu and C. Ababei, Improving simulation eficiency for circuit-level power estimation, IEEE Int. Symposium on Circuits and Systems (ISCAS), 2000.

Educational and outreach papers
[C3] C. Ababei and S.C. Schneider, Arduino to the rescue: swaying undecided freshmen engineering students to electrical and computer engineering, ASEE Midwest Section Conference, Manhattan, KS, Sep. 2016.
[C2] C. Ababei and A.M. Miron, Emulating working in a company in the classroom: a case for hands-on multiple projects oriented course, ASEE Zone III Meeting, Springfield, MO, Sep. 2015.
[C1] C. Ababei and A.M. Miron, Addressing early the gender gap in electrical engineering via summer camps for girls, ASEE North Midwest Section Conference, Fargo, ND, Oct. 2013.

Publications before 1999
[J3] C. Orita and C. Ababei, Control circuit for forcing the uninterrupted optimum regime in the inductive transfer DC-DC converters. Iasi Polytechnic Institute Bulletin, Romania, 1999.
[J2] C. Orita and C. Ababei, Isolated base drive control circuit for high power switching BJTs. Iasi Polytechnic Institute Bulletin, Romania, 1999.
[J1] C. Orita and C. Ababei, Isolated gate drive control circuit for high power switching devices. Iasi Polytechnic Institute Bulletin, Romania, 1999.
[C5] C. Ababei and M. Derevlean, On passive overunity-gain network synthesis and their use into oscillators. SCS99, Iasi , Romania, July 1999.
[C4] M. Derevlean, L. Turic, and C. Ababei, On the amplitude stability of the most common amplitude limiting networks. SCS99, Iasi, Romania, July 1999.
[C3] C. Orita and C. Ababei, Isolated gate driving circuit for high power switching MOSs. SCS99, Iasi, Romania, July 1999.
[C2] M. Derevlean and C. Ababei, A new method for electrolytic capacitors measuring. ETC98, Timisoara, Romania, Sept. 1998.
[C1] C. Orita and C. Ababei, Full controlled DC-DC converter with capacitive load. JSAEM, Japan, Nov. 1998.

Theses
[T9] Ian James Barge, Network-on-Chip Based H.264 Video Decoder on a Field Programmable Gate Arrays, M.Sc. Thesis, Dept. of Electrical and Computer Engineering, Marquette University, Milwaukee, WI, 2017.
[T8] Nathan Zimmerman, Flight Control and Hardware Design of Multi-rotor Systems, M.Sc. Thesis, Dept. of Electrical and Computer Engineering, Marquette University, Milwaukee, WI, 2016.
[T7] Alexandre Yasuo Yamamoto, A New Method for Dynamic Reliability Management for Chip Multiprocessors, M.Sc. Thesis, Dept. of Electrical and Computer Engineering, North Dakota State University, Fargo, ND, 2014.
[T6] Hamed Sajjadi Kia, Fault Tolerant and Adaptive Systems with Focus on Networks-on-Chip, Ph.D. Thesis, Dept. of Electrical and Computer Engineering, North Dakota State University, Fargo, ND, 2014.
[T5] Kianoosh Karami, Implementation of Bus-based and NoC-based MP3 Decoders on FPGAs, M.Sc. Thesis, Dept. of Electrical and Computer Engineering, North Dakota State University, Fargo, ND, 2011.
[T4] Syed Shihab Ullah, Solution Processing Electronics Using Si6H12 Inks: Poly-Si TFT's and Co-Si MOS Capacitors, M.Sc. Thesis, Dept. of Electrical and Computer Engineering, North Dakota State University, Fargo, ND, 2011.
[T3] Cristinel Ababei, Design automation for physical synthesis of VLSI circuits and FPGAs, Ph.D. Thesis, Dept. of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, 2004.
[T2] Cristinel Ababei, Chaotic communication schemes, M.Sc. Thesis, Dept. of Electronics and Telecommunications, Technical University "Gh. Asachi" of Iasi, 1998.
[T1] Cristinel Ababei, Design and implementation of a low-voltage low-power current-mode current amplifier, B.Sc. Final Project Report, Dept. of Electronics and Telecommunications, Technical University "Gh. Asachi" of Iasi, 1996.