| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| pulse_debug_reset |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pulse_warm_reset |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pulse_cold_reset |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| hps_reset_inst |
2 |
1 |
0 |
1 |
3 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|rst_controller_001|rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|rst_controller_001|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|rst_controller_001|rst_controller_001 |
33 |
32 |
0 |
32 |
2 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|rst_controller_001 |
33 |
32 |
0 |
32 |
2 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|rst_controller|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|rst_controller|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|rst_controller|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|irq_mapper_002 |
3 |
31 |
2 |
31 |
32 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|irq_mapper_001 |
2 |
32 |
2 |
32 |
32 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|irq_mapper |
3 |
31 |
2 |
31 |
32 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_rd_rsp_width_adapter |
165 |
3 |
2 |
3 |
124 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_wr_rsp_width_adapter |
165 |
3 |
2 |
3 |
124 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_rd_cmd_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
44 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_rd_cmd_width_adapter |
129 |
4 |
0 |
4 |
160 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_wr_cmd_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
44 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_wr_cmd_width_adapter |
129 |
4 |
0 |
4 |
160 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|rsp_mux|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|rsp_mux|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|rsp_mux |
249 |
0 |
0 |
0 |
125 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|rsp_demux_001 |
126 |
1 |
2 |
1 |
124 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|rsp_demux |
126 |
1 |
2 |
1 |
124 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|cmd_mux_001 |
126 |
0 |
2 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|cmd_mux |
126 |
0 |
2 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|cmd_demux |
128 |
4 |
2 |
4 |
247 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_only_master_master_limiter |
250 |
1 |
1 |
1 |
249 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|router_002|the_default_decode |
0 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|router_002 |
160 |
0 |
2 |
0 |
160 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|router_001|the_default_decode |
0 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|router_001 |
160 |
0 |
2 |
0 |
160 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|router|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|router |
124 |
0 |
3 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_agent|read_rsp_fifo |
200 |
41 |
0 |
41 |
157 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_agent|write_rsp_fifo |
200 |
41 |
0 |
41 |
157 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_agent|read_burst_uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_agent|check_and_align_address_to_size |
46 |
9 |
2 |
9 |
35 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_0_f2h_axi_slave_agent |
412 |
30 |
23 |
30 |
528 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_only_master_master_agent |
201 |
47 |
88 |
47 |
156 |
47 |
47 |
47 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1|hps_only_master_master_translator |
116 |
13 |
2 |
13 |
109 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_1 |
164 |
0 |
1 |
0 |
246 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
70 |
1 |
2 |
1 |
69 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|avalon_st_adapter |
70 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter|check_and_align_address_to_size |
46 |
9 |
2 |
9 |
35 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter |
181 |
3 |
0 |
3 |
140 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
44 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter |
145 |
4 |
0 |
4 |
176 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_004|arb|adder |
20 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_004|arb |
9 |
0 |
4 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_004 |
698 |
0 |
0 |
0 |
144 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_003|arb|adder |
20 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_003|arb |
9 |
0 |
4 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_003 |
698 |
0 |
0 |
0 |
144 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_002|arb|adder |
16 |
8 |
0 |
8 |
8 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_002|arb |
8 |
0 |
4 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_002 |
559 |
0 |
0 |
0 |
143 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux_001 |
178 |
0 |
2 |
0 |
176 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_mux |
178 |
0 |
2 |
0 |
176 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_demux_006 |
143 |
4 |
2 |
4 |
279 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_demux_005 |
143 |
4 |
2 |
4 |
279 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_demux_004 |
143 |
4 |
2 |
4 |
279 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_demux_003 |
144 |
9 |
2 |
9 |
418 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_demux_002 |
142 |
1 |
2 |
1 |
140 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_demux_001 |
144 |
9 |
2 |
9 |
418 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|rsp_demux |
180 |
9 |
2 |
9 |
526 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_006|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_006|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_006 |
281 |
0 |
0 |
0 |
141 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_005|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_005|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_005 |
281 |
0 |
0 |
0 |
141 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_004|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_004|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_004 |
281 |
0 |
0 |
0 |
141 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_003|arb|adder |
12 |
3 |
0 |
3 |
6 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_003|arb |
7 |
0 |
1 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_003 |
420 |
0 |
0 |
0 |
142 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_002 |
142 |
0 |
2 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_001|arb|adder |
12 |
3 |
0 |
3 |
6 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_001|arb |
7 |
0 |
1 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux_001 |
420 |
0 |
0 |
0 |
142 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux|arb|adder |
12 |
3 |
0 |
3 |
6 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux|arb |
7 |
0 |
1 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_mux |
528 |
0 |
0 |
0 |
178 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_demux_004 |
152 |
25 |
4 |
25 |
696 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_demux_003 |
152 |
25 |
4 |
25 |
696 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_demux_002 |
151 |
16 |
5 |
16 |
557 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_demux_001 |
178 |
1 |
2 |
1 |
176 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|cmd_demux |
178 |
1 |
2 |
1 |
176 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
35 |
0 |
2 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
40 |
5 |
0 |
5 |
34 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
35 |
0 |
2 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
40 |
5 |
0 |
5 |
34 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
35 |
0 |
2 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
40 |
5 |
0 |
5 |
34 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
35 |
0 |
2 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
40 |
5 |
0 |
5 |
34 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
35 |
0 |
2 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
40 |
5 |
0 |
5 |
34 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_burst_adapter |
142 |
0 |
0 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
35 |
0 |
2 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
40 |
5 |
0 |
5 |
35 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
178 |
0 |
0 |
0 |
176 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter |
178 |
0 |
0 |
0 |
176 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|hps_0_h2f_lw_axi_master_rd_limiter |
282 |
0 |
0 |
0 |
286 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|hps_0_h2f_lw_axi_master_wr_limiter |
282 |
0 |
0 |
0 |
286 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|fpga_only_master_master_limiter |
282 |
0 |
0 |
0 |
286 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_011|the_default_decode |
0 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_011 |
135 |
0 |
2 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_010|the_default_decode |
0 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_010 |
135 |
0 |
2 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_009|the_default_decode |
0 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_009 |
135 |
0 |
2 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_008|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_008 |
135 |
0 |
2 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_007|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_007 |
135 |
0 |
2 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_006|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_006 |
135 |
0 |
2 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_005|the_default_decode |
0 |
14 |
0 |
14 |
14 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_005 |
171 |
0 |
2 |
0 |
176 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_004|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_004 |
135 |
0 |
5 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_003|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_003 |
135 |
0 |
5 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_002|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_002 |
135 |
0 |
5 |
0 |
140 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_001|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router_001 |
171 |
10 |
5 |
10 |
176 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|router |
171 |
10 |
5 |
10 |
176 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_agent_rsp_fifo |
175 |
39 |
0 |
39 |
134 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_agent |
350 |
39 |
44 |
39 |
378 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_agent_rsp_fifo |
175 |
39 |
0 |
39 |
134 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_agent |
350 |
39 |
44 |
39 |
378 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_agent_rsp_fifo |
175 |
39 |
0 |
39 |
134 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_agent |
350 |
39 |
44 |
39 |
378 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_agent_rsp_fifo |
175 |
39 |
0 |
39 |
134 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_agent |
350 |
39 |
44 |
39 |
378 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|intr_capturer_0_avalon_slave_0_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|intr_capturer_0_avalon_slave_0_agent_rsp_fifo |
175 |
39 |
0 |
39 |
134 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|intr_capturer_0_avalon_slave_0_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|intr_capturer_0_avalon_slave_0_agent |
350 |
39 |
44 |
39 |
378 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo |
175 |
39 |
0 |
39 |
134 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent |
350 |
39 |
44 |
39 |
378 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_agent_rdata_fifo |
111 |
41 |
0 |
41 |
68 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo |
211 |
39 |
0 |
39 |
170 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_agent |
486 |
72 |
76 |
72 |
519 |
72 |
72 |
72 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|hps_0_h2f_lw_axi_master_agent|align_address_to_size |
50 |
11 |
1 |
11 |
34 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|hps_0_h2f_lw_axi_master_agent |
457 |
103 |
227 |
103 |
332 |
103 |
103 |
103 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|fpga_only_master_master_agent |
217 |
58 |
104 |
58 |
167 |
58 |
58 |
58 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size |
50 |
2 |
1 |
2 |
35 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|hps_0_h2f_axi_master_agent |
583 |
130 |
267 |
130 |
436 |
130 |
130 |
130 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|input_switch_s1_translator |
115 |
6 |
33 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_led_s1_translator |
115 |
6 |
33 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|output_seven_segment_s0_translator |
115 |
5 |
24 |
5 |
76 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|sysid_qsys_control_slave_translator |
115 |
6 |
31 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|intr_capturer_0_avalon_slave_0_translator |
115 |
6 |
31 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator |
115 |
5 |
34 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|onchip_memory2_0_s1_translator |
184 |
7 |
19 |
7 |
154 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0|fpga_only_master_master_translator |
116 |
13 |
2 |
13 |
109 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|mm_interconnect_0 |
698 |
0 |
1 |
0 |
405 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|sysid_qsys |
3 |
15 |
2 |
15 |
32 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment|seven_segment_implementation_inst|pwm_controller_inst |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment|seven_segment_implementation_inst|bcd_converter_inst5 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment|seven_segment_implementation_inst|bcd_converter_inst4 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment|seven_segment_implementation_inst|bcd_converter_inst3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment|seven_segment_implementation_inst|bcd_converter_inst2 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment|seven_segment_implementation_inst|bcd_converter_inst1 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment|seven_segment_implementation_inst|bcd_converter_inst0 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment|seven_segment_implementation_inst |
44 |
33 |
13 |
33 |
75 |
33 |
33 |
33 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_seven_segment |
44 |
0 |
0 |
0 |
75 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|output_led |
38 |
22 |
22 |
22 |
42 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|onchip_memory2_0|the_altsyncram|auto_generated |
88 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|onchip_memory2_0 |
92 |
1 |
1 |
1 |
64 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|intr_capturer_0 |
36 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|input_switch |
14 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|p2b_adapter |
14 |
8 |
2 |
8 |
20 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|b2p_adapter |
22 |
0 |
2 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|transacto|p2m |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|transacto |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|p2b |
22 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|b2p |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|fifo |
53 |
41 |
0 |
41 |
10 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|timing_adt |
12 |
0 |
3 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser |
14 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover |
12 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming |
20 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|node |
4 |
3 |
0 |
3 |
8 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master|jtag_phy_embedded_in_jtag_master |
38 |
27 |
0 |
27 |
11 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_only_master |
36 |
1 |
0 |
1 |
71 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|dll |
2 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|oct |
1 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|c0 |
228 |
173 |
8 |
173 |
280 |
173 |
173 |
173 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|seq |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].uclk_generator |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad |
7 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad |
37 |
1 |
0 |
1 |
6 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad |
19 |
1 |
0 |
1 |
3 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad |
91 |
1 |
0 |
1 |
15 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[24].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[23].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[22].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[21].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[20].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[19].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[18].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[17].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[16].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[15].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[14].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[13].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[12].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[11].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[10].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[9].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[8].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[7].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[6].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[5].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[4].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[3].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[2].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[1].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[0].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads |
118 |
0 |
5 |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads |
633 |
58 |
118 |
58 |
220 |
58 |
58 |
58 |
40 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|memphy_ldc |
10 |
0 |
1 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy |
975 |
1 |
2 |
1 |
366 |
1 |
1 |
1 |
40 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|p0 |
878 |
545 |
0 |
545 |
130 |
545 |
545 |
545 |
40 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst|pll |
2 |
1 |
2 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border|hps_sdram_inst |
1 |
0 |
0 |
0 |
31 |
0 |
0 |
0 |
40 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io|border |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|hps_io |
12 |
0 |
0 |
0 |
46 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0|fpga_interfaces |
474 |
0 |
0 |
0 |
457 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|hps_0 |
486 |
0 |
0 |
0 |
503 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|p2b_adapter |
14 |
8 |
2 |
8 |
20 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|b2p_adapter |
22 |
0 |
2 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|transacto|p2m |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|transacto |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|p2b |
22 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|b2p |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|fifo |
53 |
41 |
0 |
41 |
10 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|timing_adt |
12 |
0 |
3 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser |
14 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover |
12 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming |
20 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|node |
4 |
3 |
0 |
3 |
8 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master |
38 |
27 |
0 |
27 |
11 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst|fpga_only_master |
36 |
1 |
0 |
1 |
71 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| soc_system_inst |
55 |
4 |
0 |
4 |
99 |
4 |
4 |
4 |
69 |
0 |
0 |
0 |
0 |