Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst_soc_system|rst_controller_001|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
inst_soc_system|rst_controller_001|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
inst_soc_system|rst_controller_001 33 31 0 31 1 31 31 31 0 0 0 0 0
inst_soc_system|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
inst_soc_system|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
inst_soc_system|rst_controller 33 31 0 31 2 31 31 31 0 0 0 0 0
inst_soc_system|mm_interconnect_1|avalon_st_adapter_003|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|avalon_st_adapter_003 38 0 0 0 37 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|avalon_st_adapter_002|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|avalon_st_adapter_002 38 0 0 0 37 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|avalon_st_adapter_001|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|avalon_st_adapter_001 38 0 0 0 37 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|avalon_st_adapter|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|avalon_st_adapter 38 0 0 0 37 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_mux_001|arb|adder 16 8 0 8 8 8 8 8 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_mux_001|arb 8 0 4 0 4 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_mux_001 487 0 0 0 125 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_mux|arb|adder 16 8 0 8 8 8 8 8 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_mux|arb 8 0 4 0 4 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_mux 487 0 0 0 125 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_demux_003 125 4 2 4 243 4 4 4 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_demux_002 125 4 2 4 243 4 4 4 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_demux_001 125 4 2 4 243 4 4 4 0 0 0 0 0
inst_soc_system|mm_interconnect_1|rsp_demux 125 4 2 4 243 4 4 4 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_003|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_003|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_003 245 0 0 0 123 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_002|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_002|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_002 245 0 0 0 123 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_001|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_001|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux_001 245 0 0 0 123 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_mux 245 0 0 0 123 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_demux_001 130 16 2 16 485 16 16 16 0 0 0 0 0
inst_soc_system|mm_interconnect_1|cmd_demux 130 16 2 16 485 16 16 16 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 124 0 0 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_burst_adapter 124 0 0 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 124 0 0 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_burst_adapter 124 0 0 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 124 0 0 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_burst_adapter 124 0 0 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 124 0 0 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_burst_adapter 124 0 0 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|hps_0_h2f_lw_axi_master_rd_limiter 246 0 0 0 247 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|hps_0_h2f_lw_axi_master_wr_limiter 246 0 0 0 247 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_005|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_005 120 0 2 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_004|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_004 120 0 2 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_003|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_003 120 0 2 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_002|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_002 120 0 2 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_001|the_default_decode 0 6 0 6 6 6 6 6 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router_001 120 0 4 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router|the_default_decode 0 6 0 6 6 6 6 6 0 0 0 0 0
inst_soc_system|mm_interconnect_1|router 120 0 4 0 122 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_agent_rsp_fifo 160 39 0 39 119 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_agent 317 39 41 39 337 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_agent_rsp_fifo 160 39 0 39 119 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_agent 317 39 41 39 337 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_agent_rsp_fifo 160 39 0 39 119 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_agent 317 39 41 39 337 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_agent_rsp_fifo 160 39 0 39 119 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_agent 317 39 41 39 337 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_1|hps_0_h2f_lw_axi_master_agent|align_address_to_size 38 0 1 0 23 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_1|hps_0_h2f_lw_axi_master_agent 421 87 191 87 302 87 87 87 0 0 0 0 0
inst_soc_system|mm_interconnect_1|button_pio_s1_translator 104 6 22 6 36 6 6 6 0 0 0 0 0
inst_soc_system|mm_interconnect_1|dipsw_pio_s1_translator 104 6 22 6 36 6 6 6 0 0 0 0 0
inst_soc_system|mm_interconnect_1|led_pio_s1_translator 104 6 22 6 70 6 6 6 0 0 0 0 0
inst_soc_system|mm_interconnect_1|sysid_qsys_control_slave_translator 104 6 20 6 35 6 6 6 0 0 0 0 0
inst_soc_system|mm_interconnect_1 287 0 0 0 107 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|avalon_st_adapter|error_adapter_0 70 1 2 1 69 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|avalon_st_adapter 70 0 0 0 69 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|rsp_mux_001 167 0 2 0 165 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|rsp_mux 167 0 2 0 165 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|rsp_demux 168 4 2 4 329 4 4 4 0 0 0 0 0
inst_soc_system|mm_interconnect_0|cmd_mux|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_0|cmd_mux|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|cmd_mux 331 0 0 0 166 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|cmd_demux_001 167 1 2 1 165 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|cmd_demux 167 1 2 1 165 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 19 1 0 1 9 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 18 2 0 2 9 2 2 2 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 35 0 2 0 8 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 8 0 0 0 8 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 38 5 0 5 33 5 5 5 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 167 0 0 0 165 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter 167 0 0 0 165 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|router_002|the_default_decode 0 4 0 4 4 4 4 4 0 0 0 0 0
inst_soc_system|mm_interconnect_0|router_002 165 0 2 0 165 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|router_001|the_default_decode 0 3 0 3 3 3 3 3 0 0 0 0 0
inst_soc_system|mm_interconnect_0|router_001 165 3 3 3 165 3 3 3 0 0 0 0 0
inst_soc_system|mm_interconnect_0|router|the_default_decode 0 3 0 3 3 3 3 3 0 0 0 0 0
inst_soc_system|mm_interconnect_0|router 165 3 3 3 165 3 3 3 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_agent_rdata_fifo 111 41 0 41 68 41 41 41 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo 205 39 0 39 164 39 39 39 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor 56 1 0 1 54 1 1 1 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_agent 469 72 71 72 505 72 72 72 0 0 0 0 0
inst_soc_system|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size 48 0 1 0 33 0 0 0 0 0 0 0 0
inst_soc_system|mm_interconnect_0|hps_0_h2f_axi_master_agent 561 120 245 120 424 120 120 120 0 0 0 0 0
inst_soc_system|mm_interconnect_0|onchip_memory2_0_s1_translator 182 7 17 7 154 7 7 7 0 0 0 0 0
inst_soc_system|mm_interconnect_0 277 0 0 0 186 0 0 0 0 0 0 0 0
inst_soc_system|sysid_qsys 3 15 2 15 32 15 15 15 0 0 0 0 0
inst_soc_system|onchip_memory2_0|the_altsyncram|auto_generated 88 0 0 0 64 0 0 0 0 0 0 0 0
inst_soc_system|onchip_memory2_0 91 0 1 0 64 0 0 0 0 0 0 0 0
inst_soc_system|led_pio 38 22 22 22 42 22 22 22 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|dll 2 0 0 0 7 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|oct 1 0 0 0 32 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|c0 228 173 8 173 280 173 173 173 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|seq 0 0 0 0 0 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].uclk_generator 1 0 0 0 2 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated 3 0 0 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad 7 1 0 1 1 1 1 1 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad 37 1 0 1 6 1 1 1 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad 19 1 0 1 3 1 1 1 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad 91 1 0 1 15 1 1 1 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[24].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[23].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[22].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[21].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[20].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[19].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[18].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[17].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[16].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[15].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[14].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[13].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[12].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[11].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[10].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[9].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[8].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[7].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[6].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[5].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[4].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[3].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[2].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[1].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[0].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads 118 0 5 0 27 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads 633 58 118 58 220 58 58 58 40 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|memphy_ldc 10 0 1 0 4 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy 975 1 2 1 366 1 1 1 40 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|p0 878 545 0 545 130 545 545 545 40 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst|pll 2 1 2 1 12 1 1 1 0 0 0 0 0
inst_soc_system|hps_0|hps_io|border|hps_sdram_inst 1 0 0 0 31 0 0 0 40 0 0 0 0
inst_soc_system|hps_0|hps_io|border 0 0 0 0 0 0 0 0 0 0 0 0 0
inst_soc_system|hps_0|hps_io 12 0 0 0 46 0 0 0 69 0 0 0 0
inst_soc_system|hps_0|fpga_interfaces 166 0 0 0 367 0 0 0 0 0 0 0 0
inst_soc_system|hps_0 178 0 0 0 413 0 0 0 69 0 0 0 0
inst_soc_system|dipsw_pio 14 0 0 0 32 0 0 0 0 0 0 0 0
inst_soc_system|button_pio 8 0 0 0 32 0 0 0 0 0 0 0 0
inst_soc_system 28 1 0 1 57 1 1 1 69 0 0 0 0
inst_heartbeat 1 0 0 0 1 0 0 0 0 0 0 0 0
inst_pll_sys|pll_sys_inst 2 0 0 0 3 0 0 0 0 0 0 0 0
inst_pll_sys 2 0 0 0 3 0 0 0 0 0 0 0 0