---april.23.2026
cristinel.ababei

Dscription:
--This is the VHDL description & implementation on DE1-SoC FPGA board of a simple up/down counter.
--The folder "counter_up_down_7seg/" is the entire Intel Altera Quartus project (includes pin assignment file as well). 
--The counter counts between -31...+31 only.
--The count value is displayed on 7-segment LED displays.
