Reading

Introduction
    1) SoC. Embedded systems characteristics and applications. Design flows. Design and technology scaling/trends.
Platform and architectures
    2) Communication-based design. Networks-on-Chip (NoCs).
System modeling and specification languages
    3) System modeling - Models of computation.
    4) Specification languages
Performance abstraction
    5) NoC performance analysis. Stochastic modeling. Workload/traffic characterization.
System synthesis and optimization
    6) HW/SW co-design
    7) Mapping
    8) Buffer sizing. Routing issues in NoCs .
    9) Dynamic power management. Dynamic voltage and frequency scaling (DVFS). VFI design.
    10) Thermal management.
    11) Reliable and fault-tolerant on-chip communication. Variability-aware design.
    12) 3D integration. Reconfigurability and testing.
    13) Platform based design.
    14) RF, wireless, and photonic NoCs.


Introduction

 1) SoC. Embedded systems characteristics and applications. Design flows. Design and technology scaling/trends.

[*] Slides (pdf, ppt)
[*] A. Gerstlauer, C. Haubelt, A.D. Pimentel, Todor Stefanov, D.D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517-1530, Oct. 2009.
[*] G. De Micheli, "An Outlook on Design Technologies for Future Integrated Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 6, pp. 777-790, June 2009.
[*] S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, no. 4, pp. 23-29, Jul.-Aug. 1999.
[*] R. Ho, K.W. Mai, M.A. Horowitz, "The future of wires," Proceedings of the IEEE, vol. 89, no. 4,  pp. 490-504, Apr. 2001.
[*] Introduction presentation of ECE-249 at Berkeley:
http://chess.eecs.berkeley.edu/design/2010/lectures/IntroductionEE249_10.pdf
[*] The introduction presentation of CSE-237D at UCSD:
http://haduken.ucsd.edu/cse237d/topic01.ppt

Additional references:
[] Robert Brayton and Jason Cong, "NSF Workshop on EDA: Past, Present, and Future (Part 1)," IEEE Design and Test of Computers, 2010.
[] Robert Brayton and Jason Cong, "NSF Workshop on EDA: Past, Present, and Future (Part 2)," IEEE Design and Test of Computers, 2010.
[] R. Ernst, "Codesign of Embedded Systems: Status and Trends," IEEE Design & Test of Computers, June 1998.
[] A. Sangiovanni-Vincentelli, "Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design," Proc. IEEE, vol. 95, no. 3, Mar. 2007.
[] T. Henzinger, J. Sifakis, "The Embedded Systems Design Challenge," Invited Paper FM06.
[] Alberto Sangiovanni-Vincentelli, "The Tides of EDA," IEEE Design and Test of Computers, Nov.-Dec. 2003.
[] Jan Rabaey, Sharad Malik, "Challenges And Solutions for Late and Post Silicon Design," IEEE Design & Test of Computers, vol. 25, no. 4. pp. 296-302, 2008.
[] R. Marculescu, U.Y. Ogras, N.H. Zamora, "Computation and Communication Refinement for Multiprocessor SoC Design: A System-Level Perspective," ACM Trans. on Design Automation of Electronic Systems, Special Issue on Novel Paradigms in System-Level Design, vol. 11, no.3, pp. 564-592, July 2006.
[] V. De, S. Borkar, "Technology and design challenges for low power and high performance microprocessors," Int. Symposium on Low Power Electronics and Design, pp. 163-168, 1999.
[] Borivoje Nikolic, "Design in the Power-Limited Scaling Regime," IEEE. Trans. on Electron Devices, vol. 55, no. 1, pp. 71-83, Jan. 2008.
[] M. White, Y. Chen, "Scaled CMOS Technology Reliability Users Guide," Technical Report, JPL, Mar. 2008.
[] Mark Horowitz, "VLSI Scaling for Architects", PPT, Stanford University.


Platform and architectures

 2) Communication-based design. Networks-on-Chip (NoCs).

[*] Slides (pdf, ppt)
[*] R. Marculescu, U.Y. Ogras, L.-S. Peh, N.E. Jerger, Y. Hoskote, "Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 1, pp. 3-21, Jan. 2009.
[*] R. Marculescu and P. Bogdan, "The Chip Is the Network: Toward a Science of Network-on-Chip Design," Foundations and Trends® in Electronic Design Automation, vol. 2:, no. 4, pp. 371-461, 2009.
[*] D. Atienza, F. Angiolini, S. Murali, A. Pullini, L. Benini, G. De Micheli, "Network-On-Chip Design and Synthesis Outlook,"  Integration-The VLSI journal, vol. 41, no. 3, pp. 340-359, 2008.

Additional references:
[] L.P. Carloni, P. Pande, Y. Xie, "Networks-on-Chip in Emerging Interconnect Paradigms: Advantages and Challenges," Third International Symposium on Networks-on-Chip (NOCS), 2009.
[] L. Benini, G. De Micheli, "Networks on Chip: A new paradigm for component-based MPSoC design," in A. Jerrraya and W. Wolf Editors, Multiprocessors Systems on Chips, Morgan Kaufman, 2004, pp. 49-80.
[] N, Genko, D. Atienza, G. De Micheli, L. Benini, "Feature-NoC emulation: a tool and design flow for MPSoC," IEEE Circuits and Systems Magazine, vol. 7, pp. 42-51, 2007.
[] G. De Micheli, L. Benini, Networks on Chip, Morgan Kaufmann, 2006.
[] William Dally, Brian Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann Publishers Inc., 2003.

[] http://www.design-reuse.com/articles/10496/a-comparison-of-network-on-chip-and-busses.html
[] Network-on-Chip Blog for info on NoCs, tools, opinions and more: http://networkonchip.wordpress.com


System modeling and specification languages

 3) System modeling - Models of computation.

[*] Slides (pdf, ppt)
[*] E.A. Lee and S.A. Seshia, Introduction to Embedded Systems - A Cyber-Physical Systems Approach, http://LeeSeshia.org, 2011.
[*] Edward A. Lee, Alberto Sangiovanni-Vincentelli, "A Framework for Comparing Models of Computation," IEEE Transactions on CAD, vol. 17, no. 12, Dec. 1998.
[*] Axel Jantsch, Ingo Sander, "Models of computation and languages for embedded system design," IEE Proceedings on Computers and Digital Techniques, vol. 152, no. 2, pp. 114-129, March 2005.

Additional references:
[] Axel Jantsch, "Models of computation for networks on chip," International Conference on Application of Concurrency to System Design, June 2006.
[] H. Blume, T. von Sydow, D. Becker, T.G. Noll, "Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures," Journal of Systems Architecture, vol. 53, no. 8, pp. 466-476, Aug. 2007.
[] Edward A. Lee, "Absolutely Positively On Time: What Would It Take?," IEEE Computer, July 2005.
[] Alain Girault, Bilung Lee, Edward A. Lee, "Hierarchical Finite State Machines with Multiple Concurrency Models," IEEE Transactions On Computer-aided Design Of Integrated Circuits And Systems, vol. 18, no. 6, June 1999.
[] T. Murata, "Petri nets: Properties, analysis and applications," Proceedings of the IEEE, vol. 77, no. 4, pp. 541-580, Apr. 1989.
[] E.A. Lee, T. Park, "Dataflow Process Networks," Procedings of the IEEE, vol. 83, pp. 773-799, 1995.
[] G. Kahn, "The semantics of a simple language for parallel programming," Information Processing, pp.471-475, 1974.
[] E.A. Lee, D.G. Messerschmitt, "Synchronous Data Flow," Proc. of the IEEE, September, 1987.
[] http://ptolemy.eecs.berkeley.edu/index.htm

4) Specification languages

[*] Slides (pdf, ppt)
[*] Functional Specification for SystemC 2.0, Version 2.0-Q, April 5, 2002.
[*] D. Harel, Statecharts: A Visual formalism for Complex Systems, Sci. Comput. Programming 8, pp. 231-274, 1987.
[*] Elvinia Riccobene, Patrizia Scandurra, Sara Bocchio, Alberto Rosti, Luigi Lavazza, Luigi Mantellini, SystemC/C-based model-driven design for embedded systems, Transactions on Embedded Computing Systems (TECS) , 8(4), July 2009.
[*] Tero Kangas et al., UML-based multiprocessor SoC design framework, Transactions on Embedded Computing Systems (TECS), vol. 5, no. 2, May 2006.
[*] Kai Huang, Sang-il Han, Katalin Popovici, Lisane Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-lk Chae, Luigi Carro, Ahmed Amine Jerraya, Simulink-based MPSoC design flow: case study of Motion-JPEG and H.264, DAC, June 2007.

http://www.systemc.org/home
http://www.systemverilog.org
http://www.uml.org


Performance abstraction

 5) NoC performance analysis. Stochastic modeling. Workload/traffic characterization.

[*] Slides (pdf, ppt)
[*] Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, N. Vijaykrishnan, Chita R. Das, Design and analysis of an NoC architecture from performance, reliability and energy perspective, ANCS, 2005.
[*] Umit Y. Ogras, Radu Marculescu, Analytical router modeling for networks-on-chip performance analysis, DATE, 2007.
[*] Nikita Nikitin, Jordi Cortadella, A performance analytical model for Network-on-Chip with constant service time routers, ICCAD, 2009.
[*] Chapter 23. William James Dally, Brian Patrick Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.
[*] Terry Tao Ye, Giovanni De Micheli, Luca Benini, Analysis of power consumption on switch fabrics in network routers, DAC, 2002.
[*] Luca Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma, Interconnect modeling for improved system-level design optimization, ASP-DAC, 2008.
[*] Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha, Thermal Modeling, Characterization and Management of On-Chip Networks, MICRO, 2004.

Additional references:
[] Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh and Sharad Malik, Orion: A Power-Performance Simulator for Interconnection Networks, MICRO 35, Istanbul, Turkey, Nov. 2002.
[] Ilhan Hatirnaz, Stephane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De-Micheli, Early wire characterization for predictable network-on-chip global interconnects, SLIP, 2007.
[] Mingche Lai, Lei Gao, Nong Xiao, Zhiying Wang, An accurate and efficient performance analysis approach based on queuing model for Network on Chip, ICCAD, 2009.
[] M. Bakhouya, S. Suboh, J. Gaber, T. El-Ghazawi, Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus, NOCS, 2009.
[] Noel Eisley, Li-Shiuan Peh, High-level power analysis for on-chip networks, International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2004.
[] Mohammad Arjomand, Hamid Sarbazi-Azad, A comprehensive power-performance model for NoCs with multi-flit channel buffers, ICS, 2009.
[] Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Moraes, Application driven traffic modeling for NoCs, SBCCI, 2006.
[] G. Varatkar, R. Marculescu, On-chip Traffic Modeling and Synthesis for MPEG-2 Video Applications, in IEEE Trans. Very Large Scale Integration Systems, vol. 12, no. 1, Jan. 2004.


System synthesis and optimization

6) HW/SW co-design

[*] Slides (pdf, ppt)
[*] M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, Hardware/software codesign of embedded systems, IEEE Micro, 1994.
[*] G. De Micheli, R.K. Gupta, Hardware-Software Codesign, Proceedings of the IEEE, vol. 85, no. 3, 1997.
[*] W. Wolfe, A Decade of Hardware/Software Co-design, IEEE Computer, 2003.
[*] Marisa Lopez-Vallejo, Juan Carlos Lopez, On the hardware-software partitioning problem: System modeling and partitioning techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2003.
[*] S. Edwards, The Challenges of Hardware Synthesis from C-like Languages, DATE, 2005.

Additional references:
[] R. Gupta, G. de Micheli, A Cosynthesis Approach to Embedded System Design Automation, Journal of Design Automation of Embedded Systems, January 1996.
[] J. Henkel, Y. Li, Energy-Conscious HW/SW Partitioning of Embedded Systems: A Case Study on an MPEG-2 Encoder, CODES, 1998.
[] C.A. Valderrama, A. Changuel, P.V. Raghavan, M. Abid, T. Ben Ismail, A.A. Jerraya, A Unified Model for Co-simulation and Co-synthesis of Mixed Hardware/Software Systems, Readings in Hardware/Software Co-Design, pp. 579-583, 2002.
[] Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen, UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems, Journal of Systems Architecture, 2009.

http://www.esweek.org
http://www.design-reuse.com/articles/13331/hardware-software-partitioning-and-interface-synthesis-in-networks-on-chip.html

7) Mapping

[*] Slides (pdf, ppt)
[*] J. Hu, R. Marculescu, Energy- and Performance-Aware Mapping for Regular NoC Architectures, TCAD, vol. 24, no. 4, Apr. 2005.
[*] Srinivasan Murali, Giovanni De Micheli, SUNMAP: a tool for automatic topology selection and generation for NoCs, DAC, 2004.
[*] Cagkan Erbas, Selin Cerav-Erbas, Andy D. Pimentel, Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design, IEEE Transactions on Evolutionary Computation, 2006.
[*] M.A. Al Faruque, Rudolf Krist, Jorg Henkel, ADAM: run-time agent-based distributed application mapping for on-chip communication, DAC, 2008.
[*] Ewerson Carvalho, Ney Calazans, Fernando Moraes, Investigating Runtime Task Mapping for NoC-based Multiprocessor SoCs, IFIP VLSI SoC, 2009.
[*] S. Manolache, P. Eles, Z. Peng, Fault and energy-aware communication mapping with guaranteed latency for applications implemented on noc, DAC, 2005.

Additional references:
[] G. Ascia, V. Catania, M. Palesi, A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip, Journal of Universal Computer Science, 2006.
[] Zhonghai Lu, Lei Xia, Axel Jantsch, Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip, IEEE Workshop on Design and
[] Srinivasan Murali, Giovanni De Micheli, Bandwidth-Constrained Mapping of Cores onto NoC Architectures, DATE, 2004.
[] Srinivasan Murali, Luca Benini, Giovanni De Micheli, Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees, ASP-DAC, 2005.
[] C.-L. Chou, R. Marculescu, Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip, IEEE Trans. on CAD of Integrated Circuits and Systems, 2010.
[] Ewerson Carvalho, Ney Calazans, Fernando Moraes, Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs, IEEE International Workshop on Rapid System Prototyping, pp. 34-40, 2007.
[] Po-Chun Chang, I-Wei Wu, Jyh-Jiun Shann, Chung-Ping Chung, ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor, DAC, 2008.
[] Ewerson Carvalho and Fernando Moraes, Congestion-aware Task Mapping in Heterogeneous MPSoCs, SOC, 2008.
[] Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli, A methodology for mapping multiple use-cases onto networks on chips, DATE, 2006.

8) Buffer sizing. Routing issues in NoCs

[*] Slides (pdf, ppt)
[*] J. Hu, U.Y. Ogras, R. Marculescu, System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design, IEEE TCAD, 2006.
[*] Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Keng-Hsien Huang, An-Yeu Wu, Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks, IEEE Trans. Computers, 2008.

Additional references:
[] Liwei Wang, Yang Cao, Xiaohui Li and Xiaohu Zhu, Application Specific Buffer Allocation for Wormhole Routing Networks-on-Chip, NOCARC, 2008.
[] R. Dobkin, R. Ginosar, I. Cidon, QNoC asynchronous router with dynamic virtual channel allocation, International Symposium on Networks-on-Chip, 2007.
[] Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures, ISCA, 2008.
[] Sorin Manolache, Petru Eles, Zebo Peng, Buffer space optimisation with communication synthesis and traffic shaping for NoCs, DATE, 2006.
[] J. Duato, A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks, 1993.
[] L.M. Ni, P.K. McKinley, A survey of wormhole routing techniques in direct networks, Computer, vol. 26, no. 2, pp. 62–76, 1993.
[] J. Wu, A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model, IEEE Trans. Computers, vol. 52, no. 9, 2003.
[] Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel Kinsy, Tina Wen, Srinivas Devadas, Oblivious Routing in On-Chip Bandwidth-Adaptive Networks, MIT TR, 2009.
[] Po-Tsang Huang, Wei Hwang, An adaptive Congestion-Aware Routing Algorithm for Mesh Network-on-Chip Platform, IEEE System-on-Chip Conference (SOCC), 2009.
[] Jose Flich, Samuel Rodrigo, Jose Duato, An Efficient Implementation of Distributed Routing Algorithms for NoCs, ACM/IEEE International Symposium on Networks-on-Chip, 2008.

9) Dynamic power management. Dynamic voltage and frequency scaling (DVFS). VFI design.

[*] Slides (pdf, ppt)
[*] Xiaorui Wang, Kai Ma, and Yefu Wang, Adaptive power control with online model estimation for chip multiprocessors, IEEE Trans. on Parallel and Distributed Systems, vol. 22, no. 10, pp. 1681-1696, Oct. 2011.
[*] A.K. Mishra, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan, C.R. Das, A case for dynamic frequency tuning in on-chip networks, IEEE/ACM International Symposium on Microarchitecture, 2009.

Additional references:
[] U.Y. Ogras, R. Marculescu, D. Marculescu, E.G. Jung, Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip, IEEE TVLSI, March 2009.
[] G. Dhiman, T.S. Rosing, System-Level Power Management Using Online Learning, IEEE TCAD, 2009.
[] Li Shang, L.-S. Peh, N.K. Jha, PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks, IEEE TCAD, Jan. 2006.
[] B. Lin, A. Mallik, P.A. Dinda, G. Memik, R.P. Dick, User- and process-driven dynamic voltage and frequency scaling, Int. Symp. Performance Analysis of Systems and Software, Apr. 2009.
[] L. Guang, P. Liljeberg, E. Nigussie, H. Tenhunen, A review of dynamic power management methods in NoC under emerging design considerations, NORCHIP, 2009.

10) Thermal management.

[*] Slides (pdf, ppt)
[*] Ayse K. Coskun, Tajana Simunic Rosing, Kenny Gross, Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs, IEEE TCAD, 2009.
[*] L. Shang, L.-S. Peh, A. Kumar, N. K. Jha, Thermal modeling, characterization and management of on-chip networks, Proc. Int. Symp. Microarchitecture, Dec. 2004.

Additional references:
[] V. Hanumaiah, S.B. K. Vrudhula, K.S. Chatha, Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors, IEEE Trans. on CAD of Integrated Circuits and Systems, 2011.
[] F. Zanini, D. Atienza, and G. De Micheli, A Control Theory Approach for Thermal Balancing of MPSoC, ACM Asia and South Pacific Design Automation Conference, 2009.
[] Hwisung Jung, Peng Rong, Massoud Pedram, Stochastic modeling of a thermally-managed multi-core system, ACM/IEEE Design Automation Conference (DAC), pp. 728-733, 2008.
[] Ramkumar Jayaseelan, Tulika Mitra, Dynamic thermal management via architectural adaptation, DAC, 2009.

11) Reliable and fault-tolerant on-chip communication. Variability-aware design.

[*] Slides (pdf, ppt)
[*] Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, N. Vijaykrishnan, Chita R. Das, Design and analysis of an NoC architecture from performance, reliability and energy perspective, ANCS, 2005.
[*] David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester, Vicis: a reliable network for unreliable silicon, DAC, 2009.
[*] S. Medardoni, M. Lajolo, D. Bertozzi, Variation tolerant NoC design by means of self-calibrating links, DATE 2008.

Additional references:
[] Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, N. Vijaykrishnan, Chita R. Das, Exploring Fault-Tolerant Network-on-Chip Architectures, International Conference on Dependable Systems and Networks (DSN), 2006.
[] Naresh R. Shanbhag, Reliable and Efficient System-on-Chip Design, IEEE Computer, 2004.
[] Carles Hernandez, Federico Silla, Vicente Santonja, Jose Duato, A new mechanism to deal with process variability in NoC links, IPDPS 2009.
[] S. Herbert, D. Marculescu, Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance, IEEE Trans. on VLSI Systems, Oct. 2009.
[] Srinivasa R. Sridhara, Naresh R. Shanbhag, Coding for System-on-Chip Networks: A Unified Framework, IEEE TVLSI, 2005.
[] Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston, A Lightweight Fault-Tolerant Mechanism for Network-on-Chip, NOCS, 2008.
[] Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Erika Cota, Marcio Kreutz, Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router, SBCCI 2009.
[] Lei Zhang  Yinhe Han  Qiang Xu  Xiao wei Li  Huawei Li, On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems, TVLSI, 2009.
[] Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Mazin S. Yousif, N. Vijaykrishnan, and Chita R. Das, A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks, ISCA, 2006.
[] Thilo Streichert, Dirk Koch, Christian Haubelt, Jurgen Teich, Modeling and design of fault-tolerant and self-adaptive reconfigurable networked embedded systems, EURASIP Journal on Embedded Systems, 2006.

12) 3D integration. Reconfigurability and testing.

[*] Slides (pdf, ppt)
[*] C. Seiculescu, S. Murali, L. Benini, G. De Micheli, "SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1987-2000, 2010.
[*] W.R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M. Steer, P.D. Franzon, Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design & Test of Computers, 2005.
[*] Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal, An FPGA design flow for reconfigurable network-based multi-processor systems on chip, DATE, 2007.
[*] Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad, Application-Aware Topology Reconfiguration for On-Chip Networks, IEEE Trans. VLSI Syst., vol. 19, no. 11, pp. 2010-2022, 2011.
[*] http://www.recoresystems.com/technology/why-reconfigurable-computing/

Additional references:
[] Brett S. Feero, Partha Pratim Pande, Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation, IEEE Transactions on Computers, 2009.
[] Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli, Synthesis of networks on chips for 3D systems on chips, ASP-DAC 2009.
[] Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das, MIRA: A Multi-layered On-Chip Interconnect Router Architecture, ISCA 2008.
[] Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Vijaykrishnan Narayanan, Mazin S. Yousif, Chita R. Das, A novel dimensionally-decomposed router for on-chip communication in 3D architectures, ISCA 2007.
[] Jason Lee, Lesley Shannon, Predicting the performance of application-specific NoCs implemented on FPGAs, FPGA 2010.
[] P.S. Bhojwani, R.N. Mahapatra, Robust Concurrent Online Testing of Network-on-Chip-Based SoCs, IEEE TVLSI 2008.
[] C. Grecu et al., Testing Network-on-Chip Communication Fabrics, IEEE TCAD, 2007.

13) Platform based design.

[*] Slides (pdf, ppt)
[*] K. Keutzer, S. Malik, R. Newton, J. Rabaey and A. Sangiovanni-Vincentelli, System Level Design: Orthogonalization of Concerns and Platform-Based Design, TCAD 2000.
[*] A. Sangiovanni-Vincentelli and G. Marting, Platform-based design and software design methodology for embedded systems, IEEE Design & Test of Computers, 2001.

Additional references:
[] Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, System Design: Traditional Concepts and New Paradigms, ICCD 1999.
[] A.L. Sangiovanni-Vincentelli, L.P. Carloni, F. De Bernardinis, M. Sgroi, Benefits and Challenges of Platform-Based Design, Design Automation Conference (DAC), 2004.
[] Ergen, S.C. Sangiovanni-Vincentelli, A. Xuening Sun Tebano, R. Alalusi, S. Audisio, G. Sabatini, M., The Tire as an Intelligent Sensor, IEEE TCAD 2009.
[] A. Pinto, L.P. Carloni, A. Sangiovanni-Vincentelli, A Methodology for Constraint-Driven Synthesis of On-Chip Communications, IEEE TCAD, 2009.
[] D. Densmore, A.V. Devender, M. Johnson, N. Sritanyaratana, A platform-based design environment for synthetic biological systems, Richard Tapia Celebration of Diversity in Computing Conference, 2009.
[] A. Pinto, A. Bonivento, A.L. Sangiovanni-Vincentelli, R. Passerone, M. Sgroi, System level design paradigms: Platform-based design and communication synthesis, ACM Trans. Design Autom. Electr. Syst., 2006.
[] N. Zamora, X. Hu, R. Marculescu, System-Level Performance/Power Analysis for Platform-Based Design of Multimedia Applications, ACM Trans. on Design Automation of Electronic Systems (TODAES), 2007.
[] Book chapters 1-3. Platform based design, Berkeley.
[] Atmel's Platform-based Methodology for System-on-Chip Design Summary, 2003. http://www.atmel.com/dyn/resources/prod_documents/doc3326.pdf
[] D. Lyonnard, S. Yoo, et al., Automatic generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip, DAC 2001.

14) RF, wireless, and photonic NoCs.

[*] Luca P. Carloni, Partha Pande, Yuan Xie, Networks-on-Chip in Emerging Interconnect Paradigms: Advantages and Challenges, NOCS, 2009.
[*] S. Deb, K. Chang, A. Ganguly and P. Pande, Comparative Performance Evaluation of Wireless and Optical NoC Architectures, Proceedings of IEEE International SOC Conference (SOCC), 2010.
Architecture (HPCA), 16-20 February, 2008.
[*] D. Zhao and Y. Wang, SD-MAC: Design and Synthesis of A Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip, IEEE Trans. on Computers (TC), Vol. 57, No. 9, pp. 1230-1245, 2008.
[*] Dominic DiTomaso, Avinash Karanth Kodi, Savas Kaya and David Matolak, iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture, IEEE Symposium on High-Performance Interconnects (Hot Interconnects), 2011.
[*] M.F. Chang et al., CMP Network-on-Chip Overlaid With MultiBand RF-Interconnect, IEEE International Symposium on High-Performance Computer
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